U.S. Pat. No. 6,064,626 (Assignee ARM Limited) discloses a peripheral bus arrangement for an integrated circuit. The preamble of the specification discloses a known bus architecture in which a system bus is used for high performance system modules and a peripheral bus is used for low power devices. The system and peripheral busses are operated at the same speed and any clock resynchronisation required due to the particular operating speed of a peripheral unit is performed at that peripheral unit. A bridge is provided for receiving processing request signals from the system bus and supplying processing request signals to the appropriate peripheral unit along with the necessary clock signals to control the operation of the peripheral unit by way of the peripheral bus. The drawback of implementing this architecture in an integrated circuit is that the current consumption is related to the operating speed(s) of the system and peripheral busses, viz. the higher the operating speed, the higher the current consumption, and the capacitance of the peripheral bus, viz. the larger the number of peripheral units connected to the peripheral bus, the higher the current consumption.
In order to reduce current consumption U.S. Pat. No. 6,064,626 discloses an architecture in which there are a system bus, one higher speed peripheral bus and at least one lower speed peripheral bus and bridge circuitry between the system bus and the peripheral busses. Peripheral units are coupled to the higher and lower speed busses on the basis of operational need with a preference being given to the lower speed bus wherever possible. As a result the current consumption is reduced compared to the known bus architecture by minimising the number of peripheral devices coupled to the higher speed peripheral bus.
In another bus architecture, designed by Philips Semiconductors, there is a system bus, termed AHB (Advanced High-performance Bus) operating at a higher clock speed (HCLK) of 78 MHz and a peripheral bus, termed the VPB bus, operating at lower clock speed (PCLK) 13 MHz. Such an architecture achieves current saving whilst having one peripheral bus rather than at least two as taught by the prior art acknowledged above. Using a HDLi (Hardware Descriptive Language Integrator) AHB to VPB bridge, access from the AHB by a register in the processor coupled to the AHB to peripheral devices coupled to the VPB bus can take up to 5 PCLK cycles. This translates to (6 cycles of HCLK per each PCLK cycle)×(5 Cycle access)=30 HCLK cycles in the worst case for a transfer. This is a long delay for the microcomputer that is driving the AHB, which delay is undesirable.